Harshitha's Blog


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DPRAM and LRU

Beginning Mor1kx formal project with DPRAM and LRU algo verification which are submodules of the instruction cache.

June 5, 2021


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Mor1kx Formal

An overview of formal verification of Mor1kx, an OpenRISC's 1000 processor IP core using yosys formal tools.

May 21, 2021